IEEE 2016 - 2017 VLSI TITLES

IEEE VLSI PROJECT TILTES 2016 - 2017

S.NO

TITLES

DOMAIN

1.      

Analyzing the Effect of Clock Jitter on Self-Oscillating Sigma Delta Modulators

 

2.      

Hyper graph Based Minimum Arborescence Algorithm for the Optimization and Reoptimization of Multiple Constant Multiplications.

 

3.      

A High-Throughput Energy-Efficient Implementation of Successive Cancellation Decoder for Polar Codes Using Combinational Logic

 

4.      

Adaptive Multibit Crosstalk-Aware Error Control Coding Scheme for On-Chip Communication

 

5.      

A Method to Design Single Error Correction Codes With Fast Decoding for a Subset of Critical Bits

 

6.      

Multiple Constant Multiplication Algorithm for High-Speed and Low-Power Design

 

7.      

CORDIC II: A New Improved CORDIC Algorithm

 

8.      

Low-Power Parallel Chien Search Architecture Using a Two-Step Approach

 

9.      

Efficient Circuit for Parallel Bit Reversal .

 

10.                         

High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels

 

11.                         

Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication

 

12.                         

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications

 

13.                         

Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems

 

14.                         

Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures

 

15.                         

One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements

 

16.                         

Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis

 

17.                         

A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes

 

18.                         

A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM

 

19.                         

Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding

 

20.                         

Ultralow-Energy Variation-Aware Design: Adder Architecture Study

 

21.                         

SRAM-Based Unique Chip Identifier Techniques .

 

22.                         

Implementing Minimum-Energy-Point Systems With Adaptive Logic

 

23.                         

On Efficient Retiming of Fixed-Point Circuits

 

24.                         

Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers

 

25.                         

Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip

 

26.                         

Concept, Design, and Implementation of Reconfigurable CORDIC

 

27.                         

A New CDMA Encoding/Decoding Method for on-Chip Communication Network

 

 



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