IEEE 2013 2012 AND OLD VLSI PROJECTS @ 3500 Rs

S.NO

                   TITLE

  DOMAIN

PRICE
(Rs)

1

A Low-Cost, Systematic Methodology for Soft Error Robustness of Logic Circuits

IEE 2013

3500

2

Error Detection in Majority Logic Decoding of Euclidean Geometry Low Density Parity Check (EG-LDPC) Codes

IEE 2013

3500

3

Area-Delay Efficient Binary Adders in QCA

IEE 2013

3500

4

Data Encoding Techniques for Reducing Energy Consumption in Network-on-Chip 

IEE 2013

3500

5

Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure

IEE 2013

3500

6

VLSI Implementation of a Low-Cost High-Quality Image Scaling Processor

IEE 2013

3500

7

A High Speed Low Power CAM With a Parity Bit and Power-Gated ML Sensing

IEE 2013

3500

8

Effective and efficient approach for power reduction by using multi-bit flip-flops

IEE 2013

3500

9

FPGA Implementation of FFT Algorithm for IEEE 802.16e (Mobile wimax)

IEE 2013

3500

10

Energy-Efficient Digital Signal Processing via Voltage-Over scaling-Based Residue Number System

IEE 2013

3500

11

Design of Testable Reversible Sequential Circuits

IEE 2013

3500

12

Glitch-Free NAND-Based Digitally Controlled delay lines

IEE 2013

3500

13

 

Low-Cost FIR Filter Designs Based on Faithfully Rounded Truncated Multiple Constant

Multiplication/Accumulation

IEE 2013

3500

14

Constant Delay Logic Style

IEE 2013

3500

15

DS-CDMA Implementation With Iterative Multiple Access Interference Cancellation

IEE 2013

3500

16

Design of Ternary Logic Combinational circuits Based on Quantum Dot Gate FETs

 

IEE 2013

3500

17

A Low-Complexity Turbo Decoder Architecture for Energy-Efficient Wireless Sensor Networks

IEE 2013

3500

18

Self-Repairing Digital System with Unified Recovery Process Inspired by Endocrine Cellular Communication

IEE 2013

3500

19

Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes

IEE 2013

3500

20

Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip

 

IEE 2013

3500

21

A Wide-Range PLL Using Self-Healing Prescaler/VCO in 65-nm CMOS

IEE 2013

3500

 22

A Built-In Repair Analyzer With Optimal Repair Rate for Word-Oriented Memories

 

IEE 2013

3500

 23

Enhanced Fault-Tolerant Network-on-Chip Architecture Using Hierarchical Agents

IEE 2013

3500

24

Pipelined Radix-2(k) Feed forward FFT Architectures

IEE 2013

3500

25

Analysis and Design of a Low-Voltage Low-Power Double-Tail Comparator

IEE 2013

3500

 

 

 

 

 

 

1

 

Efficient Majority Logic Fault Detection With

Difference-Set Codes for Memory Application

IEEETRANS(2012)

3000 Rs

2

Low-Powerand Area-Efficient Carry Select Adder

IEEETRANS(2012)

3000 Rs

3

Transactions Briefs Accumulator Based 3-Weight Pattern Generation

IEEETRANS(2012)

3000 Rs

4

On Modulo Adder Design

IEEETRANS(2012)

3000 Rs

5

Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme

IEEETRANS(2012)

3000 Rs

6

A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for Embedded Network Security

IEEETRANS(2012)

3000 Rs

7

Test Data Compression Using Efficient Bit mask and

Dictionary Selection Methods

IEE E 2010

(TRANS)

3000 Rs

8

High volume diagnosis in memory BIST based on

compressed failure data

IEE E 2010

(TRANS)

3000 Rs

9

Design and Analysis of Wave-pipelined LDPC Decoder

IEEE 2010

  (CONF)

3000 Rs

10

A Novel   Control System Processor and Its VLSI Implementation

IEEE 2008

3000 Rs

11

Exploiting Parallelism in Double Path Adders' Structure

for Increased Throughput of Floationg Point Addition

IEEE 2007

3000 Rs

12

Design of an Interconnect Architecture and Signaling

Technology for Parallelism in Communication

IEEE 2007

3000 Rs

13

Applying CDMA Technique to Network-on-Chip

IEEE 2007

3000 Rs

14

A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform

IEEE 2007

3000 Rs

 



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