Projects List

Sl no File Name Download
1 2013_IEEE Design and Implementation of an On-Chip Permutation Network for Multiprocessor System On Chip
2 2011_IEEE A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating
3 2012-1EEE On Modulo2 n#U00fe1Adder Design
4 2011_IEEE Broadside and Functional Broadside Tests forPartial-Scan Circuits
5 2010_IEEE Reconfigurable IDCT Architecture for Universal Video Decoders
6 2010_IEEE Low-Power and Area-Efficient Carry Select Adder
7 2012-1EEE A High-Accuracy Adaptive Conditional-Probability Estimator for Fixed-Width Booth Multipliers
8 2012-1EEE On the Computation of Common Test Data for Broadside and Skewed-Load Tests
9 2012-1EEE Area-Efficient Parallel FIR Digital Filter Structures forSymmetric Convolutions Based on Fast FIR Algorithm
10 2011_IEEEM ADAPTIVE POWER CONTROL Adaptive Power Control Technique on
11 2012 titles
12 2011_IEEE High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications
13 2011_ IEEE High-Accuracy Fixed-Width Modified Booth Multipliers for Lossy Applications
14 2013_IEEE Effective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops
15 2011_IEEEDesign of Sequential Elements for Low Power
16 2013_IEEE Design and Implementation of an On-Chip Permutation Network for Multiprocessor System-On-Chip BASE PAPERS
17 2011_IEEE An Ultra Low Power Baseband Transceiver IC for Wireless Body Area Network in 0
18 2011_IEEE A Reconfigurable FIR Filter Architecture to Trade Off Filter Performance for Dynamic Power Consumption
19 2011_IEEEHigh Resolution Application Specific Fault Diagnosis of FPGAs
20 2012-1EEE 2 nPattern Run-Length for Test Data Compression
21 2013_IEEE A High Speed Low Power CAM With a Parity Bit and Power Gated ML Sensingt Flip Flops
22 2012-1EEE Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
23 2011 titles
24 2011_IEEE Efficient Pattern Matching Algorithm for Memory Architecture
25 2011_IEEE Power-Efficient Explicit-Pulsed Dual-Edge Triggered Sense-Amplifier Flip-Flops
26 2013_IEEE Effective and Efficient Approach for Power Reduction by Using Multi Bit Flip Flops_BASE PAPER
27 2012-1EEE Concatenation of Functional Test Subsequences for Improved Fault Coverage
28 2012-1EEE Soft Error Sensitivity Evaluation of Microprocessors by Multilevel
29 2012-1EEE A Scalable High-Performance Virus Detection Processor Against a Large Pattern Set for
30 2012-1EEE Efficient Majority Logic Fault Detection With Difference-Set Codes for Memory Applications
31 2010_IEEE LUT Optimization for Memory-Based Computation
32 2013_IEEE A High Speed Low Power CAM With a Parity Bit and Power Gated ML Sensingt Flip Flops proposed system
33 2011_IEEEDecoding-Aware Compression of FPGA Bitstreams
34 2012-1EEE Accumulator Based 3-Weight Pattern Generation
35 2012-1EEE A True Random-Based Differential Power Analysis Countermeasure Circuit for an AES Engine
36 2012-1EEE A Multistep Tag Comparison Method for a Low-Power L2 Cache
37 2011_IEEE Design of A Novel FSM based Reconfigurable Multimode Interleaver for WLAN Application
38 2011_IEEE Partial-Scan Circuits
39 2012-1EEE Low-Power and Area-Efficient Carry Select Adder
40 2013_IEEE FPGA Implementation of FFT Algorithm for IEEE 802
41 2012-1EEE Resolution of Diagnosis Based on Transition Faults
42 2013_IEEE FPGA Implementation of FFT Algorithm for IEEE 802
43 2011_IEEE A Low-Power 64-point Pipeline FFTIFFT Processor for OFDM Applications
44 2011_IEEECMOS Full-Adders for Energy-Efficient Arithmetic Applications

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